Field of the Invention
The present invention relates to an integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells, and which has a memory unit for storing addresses of defective memory cells.
For the repair of defective memory cells, integrated semiconductor memories generally have redundant memory cells, which are usually combined to form redundant row lines or redundant column lines which can replace regular lines with defective memory cells on an address basis. In this case, the integrated memory is tested, for example by an external testing device or a self-testing device, and programming of the redundant elements is subsequently performed on the basis of a so-called redundancy analysis. A redundancy circuit then has programmable elements, for example in the form of programmable fuses, which serve for storing the address of a line to be replaced.
A semiconductor memory device is tested, for example after the production process, and is subsequently repaired. For this purpose, the addresses of those tested memory cells which were detected as defective are stored in a so-called defect address memory, in order to replace these memory cells in a subsequent step with defect-free redundant memory cells on the basis of the addresses stored. The memory device is in this case generally subjected to a number of tests. Only those memory cells that pass all of the tests are considered in this case to be operative or defect-free. If a memory cell does not pass one or more tests, it is considered to be defective and must be replaced by a defect-free redundant memory cell. In the case of semiconductor memories with a memory cell array in matrix form, which have redundant row lines or redundant column lines, instead of a single memory cell usually an entire row line or column line is replaced by corresponding redundant row lines or column lines.
Since memory cells are subjected to a number of tests, if a particular test is not passed, it must be determined whether the defect address has already been stored because of a failure of a previous test. This determination must be performed before the address of the defective memory cell is stored. If this is the case, the defect address should not be stored a second time, in order to save memory space. The defect addresses may be stored in a separate memory cell array on the chip to be tested. This additional memory cell array is then part of, for example, a self-testing device of the memory chip.
The check to be carried out to ascertain whether a memory cell has already been stored once must not influence the speed with which the memory test is carried out. For example, a parallel comparison of all of the defect addresses already stored with the current defect address, and possibly the subsequent storage of the new address, can in this case take place together in one clock cycle. However, this generally leads to the provision of a considerable amount of circuitry for the defect address memory. A serial comparison of the stored defect addresses with the current defect address is possible only if it can be ensured that the time from detecting one defective memory cell to detecting the next defective memory cell reaches a certain length. This time must be made to be of such a duration to insure that the address of a previously detected defective memory cell can be compared with all of the already stored defect addresses and the address of this detected defective memory cell can possibly be stored before another defective memory cell is detected. Since defective memory cells often occur in rapid succession in a memory cell test, in particular along row lines or column lines, the time periods described usually cannot be maintained.
As long as the number of defective memory cells is small in comparison with the memory size, a memory unit can be provided as a buffer memory, in order to decouple a test of the memory cell array and the storage of the defect addresses. This buffer memory must in this case be large enough to ensure that the addresses of memory cells detected as defective can at any time still be written to be buffer memory. The maximum size of the buffer memory to be provided can be estimated on the basis of the size of the memory to be tested and the existing number of redundant row lines and column lines. For example, all the memory cells along a column line and at the same time as many column lines as it takes to establish that there is no redundant column line available any longer for the repair of defective memory cells along a column line must be tested. This results in a relatively high storage requirement of the buffer memory to be provided. For memory devices with an in-built self-testing unit, such a solution is usually too complex.